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Bücher Englische Bücher Wissen & Bildung Naturwissenschaft, Medizin, Informatik, Technik Informatik & EDV Transistor-Level Layout of Integrated Circuits
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Transistor-Level Layout of Integrated Circuits
Jan Schneider (Broschiert, Englisch)
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Beschreibung
In this dissertation, we present the toolchain BonnCell and its underlying algorithms. It has been developed in close cooperation with the IBM Corporation and automatically generates the geometry for functional groups of 2 to approximately 50 transistors. Its input consists of a set of transistors, including properties like their sizes and their types, a specification of their connectivity, and… parameters to flexibly control the technological framework as well as the algorithms' behavior.
Using this data, the tool computes a detailed geometric realization of the circuit as polygonal shapes on 16 layers. To this end, a placement routine configures the transistors and arranges them in the plane, which is the main subject of this thesis. Subsequently, a routing engine determines wires connecting the transistors to ensure the circuit's desired functionality.
We propose and analyze a family of algorithms that arranges sets of transistors in the plane such that a multi-criteria target function is optimized. The primary goal is to obtain solutions that are as compact as possible because chip area is a valuable resource in modern techologies. In addition to the core algorithms we formulate variants that handle particularly structured instances in a suitable way.
We will show that for 90% of the instances in a representative test bed provided by IBM, BonnCell succeeds to generate fully functional layouts including the placement of the transistors and a routing of their interconnections.
Moreover, BonnCell is in wide use within IBM's groups that are concerned with transistor-level layout - a task that has been performed manually before our automation was available. Beyond the processing of isolated test cases, two large-scale examples for applications of the tool in the industry will be presented: On the one hand the initial design phase of a large SRAM unit required only half of the expected 3 month period, on the other hand BonnCell could provide valuable input aiding central decisions in the early concept phase of the new 14 nm technology generation. Dieses Produkt haben wir gerade leider nicht auf Lager.
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Technische Daten
Erscheinungsdatum
10.09.2014
Sprache
Englisch
EAN
9783737508193
Herausgeber
epubli
Sonderedition
Nein
Autor
Jan Schneider
Seitenanzahl
164
Auflage
1
Einbandart
Broschiert
Lesealter
1-99
Schlagwörter
Algorithmen, Branch and Bound, VLSI, Transistoren, Chips
Thema-Inhalt
TJFD - Elektronische Geräte und Materialien
Höhe
210 mm
Breite
14.8 cm
-.-
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