Schlagwörter
Technische Universität München, TU München, TUM, TUM School of Computation, Information and Technology, Department of Electrical Engineering, Chair of Real-Time Computer Systems, Field-programmable Gate Array, Programmable Hardware, System-on-Chip, Heterogeneous Real-time System, Networked Real-time System, Timing and Energy Constraints, End-to-end Latency, Predictability, Safety and Security, Energy Efficiency, High-speed Visual Servoing, Elektrotechnik, SG/DMA, Gigabit Ethernet, Hybrid Network Topology, In-situ Latency Monitoring, I/O-to-fabric Redirection, Multi-rail Voltage/Current Monitoring, Unified Tracing, Clock Gating, Latency-neutral Energy Optimization